Thus, a single metal interconnect layer, which is used to have bidirectional metal lines and take one mask to pattern, now typically has unidirectional metal lines and will require 3 or more conventional masks to pattern. Because isolated features can be patterned with higher resolution, cuts in the line and space patterns can then be made by multiple lithography and etch passes, a process sometimes referred to as Litho-Etch-Litho-Etch (LELE). Self-aligned multi-patterning (SAMP) schemes are employed to fabricate the dense line and space patterns, Fig. Therefore, it is necessary to use various multiple patterning technologies to create structures on the chip that are smaller than what can be patterned lithographically alone. Minimum feature sizes, defined by the tightest orthogonal half pitches in the chip, have scaled down to the point where it is no longer possible to use only single exposure lithography in high volume manufacturing (HVM). This integrated approach to power, performance, area, and cost (PPAC) scaling is the current paradigm within the semiconductor industry and has resulted in microprocessors and systems on a chip (SOC’s) comprising billions of transistors and DRAM chips comprising tens of billions of capacitors and 10 or more metal interconnect layers. 4 Over the past decade, device makers have increasingly relied upon new device geometries and new circuit architectures to continue Moore’s law style scaling that can deliver improved performance, within reasonable power limits, at a manufacturable chip area and with a reduced cost per device. High dielectric constant (high k) materials were introduced as a countermeasure, but those only provided a brief respite. 3 As gate and capacitor dielectrics scaled down deleterious leakage, currents grew to the point where it was no longer possible to make them physically thinner, while maintaining power consumption and device heating below reasonable limits. Recently, this approach has encountered fundamental roadblocks. For decades, scaling was achieved by continually making devices (and interconnects) smaller, for instance according to Dennard’s law 2 for transistors. Semiconductor integrated circuit scaling according to Moore’s law 1 has enabled a computing revolution that has transformed the way people interact with each other and the world in general.
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